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Computer Architecture Explained: What Actually Happens Inside a CPU

Hello readers, welcome back.


This is the third blog in the Basics of Computer Science series. If you skipped the first two blogs, stop here and read them first—because today we’re going deeper into the machine, and trust me, this is where 99% of engineering students get stuck. They memorize definitions but never understand what actually happens inside a CPU.

Disclaimer: i use AI tools for refining and seo optimisation, this blog is entirely human written. 


So let’s talk about the architectural brilliance behind this masterpiece we call a computer.
No fancy words. No complicated jargon. Just pure understanding.

We’ll break this into 8 parts:

  1. CPU anatomy

  2. Registers

  3. ALU + Control Unit

  4. The Instruction Cycle

  5. Pipelining

  6. Cache hierarchy

  7. RISC vs CISC

  8. CPU vs GPU architecture

Let’s begin.

STEP 1 — CPU Anatomy: What a CPU Is Actually Made Of

A CPU isn’t magic. It’s a carefully engineered combination of four major components:

1. ALU (Arithmetic Logic Unit)

This is the math department of your computer.
It does only a handful of operations:

  • addition

  • subtraction

  • AND

  • OR

  • bit shifts

  • comparisons

Yes, that’s it. No division. No multiplication. Those are all built using addition, subtraction, and logic rules.
Simple building blocks—but insanely powerful when combined with billions of clock cycles.

2. Control Unit (CU)

Think of the CU as the one giving orders.

It:

  • fetches an instruction

  • decodes it

  • tells the ALU what to do

  • manages all the data movement inside the CPU

Remove the CU and the entire CPU becomes dead silicon.

3. Registers

This is the fastest memory you’ll ever find in a computer.
Faster than cache. Faster than RAM. Faster than anything.

Registers store whatever the CPU needs right now.

Examples:

  • PC (Program Counter) → which instruction to execute next

  • SP (Stack Pointer) → where the stack currently sits

  • ACC (Accumulator) → stores results from ALU

  • General-purpose registers → R0, R1, R2, etc

If RAM is like a warehouse, registers are the items literally in your hand.

4. Buses (The Highways)

A CPU cannot scream “I need data!” into the void.
It uses buses—structured pathways.

Three of them:

Data Bus

Carries actual data between CPU, RAM, and I/O.

Address Bus

Tells the system which memory location the CPU wants.

Control Bus

Carries signals like read, write, interrupts, and status.

These buses are the nervous system that connects CPU ↔ RAM ↔ Cache ↔ everything else.

STEP 2 — What Registers Actually Do

Imagine you’re multiplying 72 × 44.
You don’t write every intermediate number on paper—you hold a few values in your mind.

Registers do exactly that.

They hold:

  • partial results

  • memory addresses

  • instruction pointers

And they do it at insane speed.

Assembly programmers love registers because you get to decide what goes where—which means peak performance with minimal overhead.

STEP 3 — ALU + CU: The Deadly Combination

The ALU is strength.
The CU is brains.

Together:

  • ALU handles all calculations

  • CU handles all decisions

The CU fetches instructions, decodes them, tells the ALU what to do, directs data to registers, and then moves to the next instruction.

This is literally the heartbeat of every computer in the world.

STEP 4 — The Instruction Cycle: The Loop Running Billions of Times Per Second

Every processor follows this same loop:

1. Fetch

Get the instruction from memory.

2. Decode

Figure out what the instruction actually wants:

  • what operation

  • which registers

  • which memory locations

3. Execute

ALU performs the operation.

4. Writeback

Store the result back into a register or RAM.

Then the Program Counter increments, and the whole loop starts again.

Your laptop is silently repeating this cycle millions to billions of times while you read this line.

STEP 5 — Pipelining: Why Modern CPUs Are Fast

Older CPUs executed one instruction at a time.
Modern CPUs overlap instructions like a factory line:

  • One instruction is being fetched

  • Another is being decoded

  • Another is being executed

  • Another is writing back

More work happening in parallel → more speed.
Simple idea. Brutal execution.

This is why a 3 GHz processor can feel far faster than “3 billion operations per second” sounds.

STEP 6 — Cache Hierarchy: L1, L2, L3

The CPU is too fast. RAM is too slow.
So engineers built layers of cache in between.

L1 Cache

  • inside each core

  • super fast

  • tiny (~32 KB)

L2 Cache

  • larger (~256 KB – 1 MB)

  • slower

  • also per-core

L3 Cache

  • huge (up to 64 MB)

  • shared between cores

  • slower than L1/L2 but still faster than RAM

Think of cache like ammunition stored near the soldier.
If the soldier had to run back to the base (RAM) every time he needed bullets, the war would be over before he returned.

STEP 7 — RISC vs CISC (The Two Mindsets)

CISC (x86 – Intel/AMD)

  • complex instructions

  • one instruction can do a lot

  • more power-hungry

  • good for desktops and servers

RISC (ARM, RISC-V, Apple Silicon)

  • simple, short instructions

  • extremely efficient

  • dominates mobile devices

  • rising fast in laptops

RISC is the future, especially with Apple’s Silicon making waves.

STEP 8 — CPU vs GPU: The Final Difference

CPU

  • few cores (4–16)

  • each core is insanely powerful

  • great for logic, branching, general tasks

Think of CPUs as a team of elite specialists.

GPU

  • thousands of tiny cores

  • built for parallelism

  • perfect for graphics, ML, and matrix operations

Think of GPUs as an army of disciplined soldiers.

That’s why GPUs dominate AI, deep learning, and any workload that relies on parallel processing.

You now understand:

  • what the CPU is made of

  • how registers work

  • how the ALU and CU operate

  • how the instruction cycle runs

  • how pipelining boosts performance

  • why caches exist

  • the mindset behind RISC vs CISC

  • why GPUs crush CPUs in parallel workloads

This is the real foundation of computer architecture—not the textbook version, but the version that actually makes sense.

If you’re enjoying this series, stick around.
The next chapters go even deeper.


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